This technical paper provides an overview of an implementation and verification of a phase locked loop (PLL) using Moku:Pro’s Multi-Instrument Mode (MiM). The reader will gain an understanding of the features of Moku Pro’s MiM and its user interface together with Moku’s powerful ability to test and verify the performance of a widely implemented system, the PLL.
Moku:Pro is an Instrument-on-Chip (IoC) test system able to run multiple instruments on a single FPGA-based hardware platform. Now, with Multi-instrument Mode, entire systems of test equipment traditionally made up of separate hardware boxes or modules can be realized on a single Moku:Pro. Utilizing dynamic reconfiguration of the FPGA, users can hot-swap instruments independently without affecting the remaining instruments in the system. Furthermore, instruments can be interconnected, and signals passed between them entirely in the digital domain within the FPGA. This enables high data rates with ultra-low latency and none of the SNR degradation that typically would result from the analog-to-digital or digital-to-analog conversions between separate hardware modules or instruments.
Multi-instrument Mode greatly expands the versatility of the Moku:Pro, realizing the potential of IoC capabilities.
Multi-instrument Mode Architecture
Figure 1: Multi-instrument mode user interface on Moku:Pro – all 4 slots empty
Figure 1 shows the starting point of building a multi-instrument system. Moku:Pro’s FPGA is divided into 4 instrument slots. Each slot represents a segment within the UltraScale+ FPGA inside Moku:Pro, and each has access to Moku:Pro’s analog inputs and outputs. Signals can be passed between these instruments in the digital domain without ever leaving the FPGA and are therefore lossless with deterministic, nanosecond-level latency. Users have the flexibility to place Moku:Pro’s individual instruments into these slots; for example, the Spectrum Analyzer, Oscilloscope, Frequency Response Analyzer, and PID Controller can be deployed simultaneously and in any combination.
Phase Locked Loop
A phase locked loop is a system that tracks the phase of an incoming signal and uses this to control the frequency of an output signal, effectively locking the frequencies together. This is useful across the spectrum of applications, from research and development to design and prototyping, all the way into the hands of test engineers. For example, a PLL is a fundamental component of radio receivers and other telecommunications, providing stable clocks for computers, synchronizing clocks, or generating frequencies at multiples of the source signal (frequency synthesis).
The most basic PLL is a phase detector followed by a low-pass filter and a voltage controlled oscillator. A VCO provides a frequency output proportional to its input voltage.
Figure 2: PLL block diagram
The phase detector takes two inputs: the external clock, and the reference or local oscillator. The phase detector (PD) output is a voltage that is dependent on the phase difference of the input clocks and is used to drive the VCO. There are different implementations of the PD. For example, a frequency mixer (or demodulator) can be used. This has the disadvantage of generating frequency spurs or harmonics and thus setting a requirement on the low-pass filter that might reduce the lock time or capture range. An alternative PD implementation would be a digitally implemented phase-frequency detector. Moku:Pro’s Phasemeter is an example of a high precision (6 μ
radian/√Hz), digital phase detector.
Moku:Pro PLL Implementation
Phase detector
We will implement a PLL on Moku:Pro and examine its operation.
First we note that a lock-in amplifier (LIA) has a demodulation stage followed by a low-pass filter. The Moku LIA can also convert the X-Y output to magnitude and phase (r-Φ) and thus we can use the LIA as a phase detector. Figure 3 shows the Moku Lock-in Amplifier user interface with the local oscillator set to 50 MHz, the demodulator followed by a lowpass filter (1 kHz), rectangular to polar conversion, and finally gain and offset functions. The phase output of the polar conversion is fed to Out A and will form our phase measurement.
Figure 3: Moku:Pro Lock-in Amplifier user interface
VCO
The VCO is implemented on Moku:Pro using a Waveform Generator. The Moku Waveform Generator can modulate the output from a variety of sources. For example, the modulation source can be another waveform generator, an internal source, or an input to the instrument. Figure 4 shows the Waveform Generator user interface. To implement the VCO the Waveform Generator is configured to generate a frequency modulated (FM) sine wave, with source of modulation set to Input A; the modulation depth is set at +- 50 kHz/V and this will ultimately determine the maximum capture range.
Figure 4: Moku:Pro Waveform Generator; FM signal
The Multi-instrument Mode inter-instrument busses are 2 Vpp, so the maximum FM deviation is +/- 50 kHz. It is also worth noting that the carrier is set to 50.05 MHz. This is a deviation 50 kHz from the lock-in’s local oscillator of 50 MHz, so that this example will need the full FM deviation range.
Multi-instrument configuration
We will now configure Multi-instrument Mode. Starting the blank configuration of Figure 1, we setup MiM to look like Figure 5.
Slot 1 contains the LIA (PD function). Slot 2 is occupied by the FM waveform generator (VCO). The output of the VCO is driven to the internal bus #2 and thus looped back to input A of the Lock-in Amplifier (PD).
Figure 5: MiM configured for PLL testing and measurement
It is helpful to be able to observe the PLL behavior in both time and frequency domains so we have deployed the Oscilloscope in slot 3 and the Spectrum Analyzer in slot 4. Both are set up to observe bus 1 (PD reference LO) and bus 2 (FM WG or VCO output). All 4 instruments operate simultaneously and independently. This is a useful setup to examine the PLL behavior; in most applications it is more typical that the VCO would supply the LO, locking to a signal supplied externally via an ADC and into input A of the LIA.
PLL operation
At initial setup, the Lock-in Amplifier is configured with its Output A turned off. The means the PD output is disabled and the Waveform Generator (WG) will output its FM signal at 50.05 MHz. Figure 6 is the user interface of the LIA in slot 1 with the built-in oscilloscope showing the LO at 50 MHz and the incoming signal on input A (the WG output) at 50.05 MHz. These signals are not locked and the incoming phase is continuously rolling past the reference LO.
Figure 6: Lock-in Amplifier with output off; PLL unlocked
Figure 7 is the user interface of the slot 3 Oscilloscope which confirms the unlocked status of the PLL. The frequencies of the VCO and reference are 50 kHz apart, and the Oscilloscope data window shows the phase delta fluctuating from +/- 180 degrees.
Figure 7: Oscilloscope with PLL unlocked
Figure 8 shows the slot 4 Spectrum Analyzer in the same unlocked PLL situation. We see the LO on channel A at 50.000 MHz and the VCO output at 50.051 MHz, a steady and fixed frequency offset
Figure 8: Spectrum Analyzer with unlocked PLL
Locking the PLL
Now we enable the Lock-in Amplifier output with one single tap on Out A. The Lock-in Amplifier output is now driving an error signal representing the instantaneous phase error between the LO and the VCO output. The WG (VCO) responds and the loop locks while the WG output tracks the LO.
Figure 9: Oscilloscope with locked PLL
Figure 9 shows the Oscilloscope in slot 3 with two locked sine waves and a steady phase difference between the LO and VCO of mean 16.65 degrees and standard deviation of 20 milli- degrees over sample size of n=10049. It is worth noting that channel A/red (reference LO from LIA) has a frequency std dev of 1.017 Hz at 50 MHz whereas the VCO shows a std dev of 3.229 Hz. This is likely due to quantization errors in the generation of the VCO output. To examine this further, the σ of the VCO output frequency was recorded for a range of FM modulation depths and therefore a range of control loop gains. The results are shown in Table 1 and Figure 10.
A deeper modulation depth (high FM deviation per volt) gives a wider locking bandwidth but lower gain. The data confirms this, and that narrower locking bandwidths improves the precision of the lock. At 10kHz/V the σ (fvco) is close to the σ (fc) This PLL performance will be investigated further in a future technical note using the precision of Moku:Pro’s Phasemeter.
Table 1: σ Fvco vs FM depth
Figure 10: σ Fvco vs FM depth
In Figure 11 the Spectrum Analyzer in slot 4 shows the VCO and LO are now locked at 50.0002 MHz, with the 200 Hz offset likely due to differing measurement algorithms of the Spectrum Analyzer vs. the Oscilloscope.
Figure 11: Spectrum Analyzer with locked PLL
Conclusion
Moku:Pro’s Multi-instrument Mode allows very flexible instrument configurations, deploying up to 4 instruments simultaneously. The instruments operate concurrently and independently of one another.
In this technical note we have implemented a PLL. This locked a VCO (implemented by Moku:Pro’s Waveform Generator) to the Lock-in Amplifier internal reference. While this is a demonstration of the principles of PLLs and the intuitive Moku:Pro user interface, a typical application would involve locking to an external signal (sampled via Moku:Pro’s ADCs) of slightly unknown frequency such as a radio carrier wave. The locked signal may well the be driven externally to Moku:Pro via its DACs.
The intuitive graphical user interface allowed us to perform this experiment in a few minutes and observe the fast lock time and lock range (+/- 50kHz). We have observed the PLL locking in both time and frequency domains and used the Oscilloscope’s data logging to record statistics, including the standard deviation of frequency of the PLL.
There are numerous applications that are enabled by such a flexible test platform. While this note and example operated entirely within one Moku:Pro, either the PD or VCO element could be an external system under test. Further, the example could be used to evaluate a design proposal, using Moku hardware to evaluate design parameters before committing to hardware.
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